U.S. Pat. No. 7,164,606 B1, which issued on Jan. 16, 2007, to Poplevine et al., discloses an all PMOS 4-transistor non-volatile memory (NVM) cell that utilizes reverse Fowler-Nordheim tunneling for programming. U.S. Pat. No. 7,164,606 is hereby incorporated by reference herein in its entirety to provide background information regarding the present invention.
Referring to FIG. 1, as disclosed in U.S. Pat. No. 7,164,606, in accordance with the method of programming an NVM array that includes all-PMOS 4-transistor NVM cells having commonly-connected floating gates, for each cell 100 in the array that is to be programmed, all of the electrodes of the cell are grounded. Then, an inhibiting voltage VN is applied to the bulk-connected source region Vr of the cell's read transistor Pr, to the commonly-connected drain, bulk and source regions Ve of the cell's erase transistor Pe, and to the drain region Dr of the read transistor Pr. The source region Vp and the drain region Dp of the cell's programming transistor Pw are grounded. The bulk Vnw of the programming transistor Pw is optional; it can be grounded or it can remain at the inhibiting voltage VN. For all cells in the NVM array that are not selected for programming, the inhibiting voltage VN is applied to the Vr, Ve and Dr electrodes and is also applied to the Vp, Dp and Vnw electrodes. The control gate voltage Vc of the cell's control transistor Pc is then swept from 0V to a maximum programming voltage Vcmax in a programming time Tprog. The control gate voltage Vc is then ramped down from the maximum programming voltage Vcmax to 0V. All electrodes of the cell and the inhibiting voltage VN are then returned to ground.
The all-PMOS 4-transistor NVM cell programming technique disclosed in the '606 patent provides advantages of both low current consumption, allowing the ability to simultaneously program a large number of cells without the need for high current power sources, and a simple program sequence. However, the 4-transistor all-PMOS NVM cell occupies a relatively large area. Thus, it would be highly desirable to have available an NVM cell having reduced area, but that maintains the benefits of low programming current.